module project3_multiplier (iClk, iReset, iReady, oDone, iMultiplier, iMultiplicand, oProduct);

input iClk, iReset, iReady;
input [7:0] iMultiplier, iMultiplicand;
output oDone;
output [15:0] oProduct;

reg [6:0] multiplicand;
reg [13:0] product;
reg [7:0] stateregister;
reg [12:0] shiftregister13;
reg [6:0] shiftregister7;

wire [6:0] inwmultiplicand,wmultiplier;
wire [13:0] wproduct;
wire [12:0] frontproduct,backproduct;
wire [6:0] frontstateregister,backstateregister; 
wire [6:0] outupperproduct,result;
wire [2:0] ALUop;
wire [12:0] winshiftregister13,woutshiftregister13;
wire [6:0] winshiftregister7,woutshiftregister7;
wire zero, overflow;
wire restart00,restart;
wire shiftright, Write;
wire wstate,wdone;
supply0 low;
supply1 high;


always @(posedge iClk) begin
multiplicand[6:0]=inwmultiplicand[6:0];
product[6:0]=wmultiplier[6:0];
product[13:7]=outupperproduct[6:0];
end

always @(posedge shiftregister) begin
product[12:0]=backproduct[12:0];
stateregister[6:0]=backstateregister[12:0];
end

always @(negedge shiftregister) begin
product[13:1]=frontproduct[12:0];
product[7:1]=frontstateregister[12:0];
end

assign backstateregister[7:0]=shiftregister7[7:0];
assign backproduct[12:0]=shiftregister13[12:0];

assign wstate=stateregister[7];

ControlSignal_Multiplier cm00(iClk,product[0],shiftright,Write);

assign ALUop[0]=low;
assign ALUop[1]=high;
assign ALUop[2]=low;

and pmand00(restart00,~iReset,~iReady);
or pmor01(restart,iReset,restart00);

Mux14to7_1bit iMwm00(iMultiplier,product[6:0],wmultiplier,restart);
Mux14to7_1bit iMcimc00(iMultiplicand,Multiplicand,inwmultiplicand,restart);
Mux14to7_1bit iMcomc00(result,product[13:7],outupperproduct,Write);

Mux26to13_1bit fpws00(shiftregister13,product[13:1],frontproduct,shiftright);

Mux14to7_1bit fsws00(shiftregister7,stateregister[7:1],frontstateregister,shiftright);

Mux2to1_1bit rws00(restart,stateregister[0],wstate,restart);

ALU_7bit_unsigned seven01(multiplicand, product[13:7], result, zero, overflow, ALUop);

xor exclusive01(oProduct[15],iMultiplier[7],iMultiplicand[7]);
assign oProduct[14]=low;
or pmor02(oProduct[13:0],product[13:0],stateregister[0]);
assign oDone=stateregister[0];

endmodule